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HY5V16CF 2 banks x 512k x 16bit synchronous dram this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.0/jun.01 description the hynix HY5V16CF is a 16,777,216-bit cmos synchronous dram, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V16CF is organized as 2banks of 524,288x16. HY5V16CF is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchron ized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and o utput volt- age levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles ini tiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a bu rst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burs t read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? single 3.3 0.3v power supply note) ? all device pins are compatible with lvttl interface ? jedec standard 60ball fd-bga with 0.65mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by udqm or ldqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency power organization interface package HY5V16CF-h 133mhz normal 2banks x 512kbits x16 lvttl 10.1x 6.4 60ball 0.65 pin -pitch fd-bga HY5V16CF-s 100mhz
HY5V16CF rev. 0.0/jun.01 2 pin configuration (16 m sdram) pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a10 address row address : ra0 ~ ra11, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details ldqm, udqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq15 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection
HY5V16CF rev. 0.0/jun.01 3 functional block diagram 512kbit x 2banks x 16 i/o synchronous dram column addr . latch & counter burst length counter refresh interval timer refresh counter dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 address register i/o control test mode mode register self refresh counter column decoder sense amp & i/o gates 512 kx16 bank 0 column decoder sense amp & i/o gates 512 kx16 bank 1 ras cas cs we udqm ldqm cke precharge overflow column active row active address[0:10] clk ba(a11) state machine row decoder row addr . latch/ predecoder auto/self refresh ref. addr .[0:11] data input/output buffers row addr . latch/ predecoder
HY5V16CF rev. 0.0/jun.01 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta=0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration 3.v il (min) is acceptable -2.0v ac pulse width with 3ns of duration ac operating condition (ta=0 to 70 c , v dd =3.3 0.3v note2 , v ss =0v) note : 1. output load to measure access time is equivalent to two ttl gates and one capacitor (50pf) for details, refer to ac/dc output circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 c sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 2.0 v 1,2 input low voltage v il v ssq - 2.0 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 50 pf 1
HY5V16CF rev. 0.0/jun.01 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v note3 ) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 parameter pin symbol min max unit input capacitance clk c i1 2 4 pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci 2 2.5 5 pf data input / output capacitance dq0 ~ dq15 c i/o 2 6.5 pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol - 0.4 v i ol = +4ma vtt =1.4v rt=250 w 50 pf output 50 pf output dc output load circuit ac output load circuit
HY5V16CF rev. 0.0/jun.01 6 dc characteristics ii (ta=0 to 70 c , v dd =3.3 0.3v note5 , v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii parameter symbol test condition speed unit note -h -s operating current i dd1 burst length=1, one bank active t rc 3 t rc (min), i ol =0ma 110 90 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 2 ma i dd2ps cke v il (max), t ck = 1 ma precharge standby current in non power down mode i dd2n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks. all other pins 3 v dd -0.2v or 0.2v 50 ma i dd2ns cke 3 v ih (min), t ck = input signals are stable. 12 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 7 ma i dd3ps cke v il (max), t ck = 5 ma active standby current in non power down mode i dd3n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks. all other pins 3 v dd -0.2v or 0.2v 50 ma i dd3ns cke 3 v ih (min), t ck = input signals are stable. 20 ma burst mode operating current i dd4 t ck 3 t ck (min), i ol =0ma all banks active cl=3 150 100 ma 1 cl=2 100 ma auto refresh current i dd5 t rrc 3 t rrc (min), all banks active 100 ma 2 self refresh current i dd6 cke 0.2v 1 ma
HY5V16CF rev. 0.0/jun.01 7 ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be measured with input signals of 1v/ns edge rate parameter symbol -h -s unit note min max min max system clock cycle time cas latency = 3 tck3 7.5 1000 10 1000 ns cas latency = 2 tck2 10 10 ns clock high pulse width tchw 3 - 3 - ns 1 clock low pulse width tclw 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 6 6 ns 2 cas latency = 2 tac2 8 - 8 ns data-out hold time toh 2.5 - 2.5 - ns data-input setup time tds 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - ns 1 address setup time tas 2 - 2 - ns 1 address hold time tah 1 - 1 - ns 1 cke setup time tcks 2 - 2 - ns 1 cke hold time tckh 1 - 1 - ns 1 command setup time tcs 2 - 2 - ns 1 command hold time tch 1 - 1 - ns 1 clk to data output in low z-time tolz 1.5 - 1 - ns clk to data output in high z-time cas latency = 3 tohz3 5.4 6 ns cas latency = 2 tohz2 ns
HY5V16CF rev. 0.0/jun.01 8 ac characteristics i note : 1. a new command can be given trrc after self refresh exit parameter symbol -h -s unit note min max min max ras cycle time operation t rc 65 - 70 - ns auto refresh t rrc 65 - 70 - ns ras to cas delay t rcd 20 - 20 - ns ras active time t ras 45 120k 50 120k ns ras precharge time t rp 20 - 20 - ns ras to ras bank active delay t rrd 15 - 20 - ns cas to cas delay t ccd 1 - 1 - clk write command to data-in delay t wtl 0 - 0 - clk data-in to precharge command t dpl 1 - 1 - clk data-in to active command t dal 4 - 3 - clk dqm to data-out hi-z t dqz 2 - 2 - clk dqm to data-in mask t dqm 0 - 0 - clk mrs to new command t mrd 1 - 1 - clk precharge to data output hi-z cas latency = 3 t proz3 3 - 3 - clk cas latency = 2 t proz2 2 - 2 - clk power down exit time t pde 1 - 1 - clk self refresh exit time t sre 1 - 1 - clk 1 refresh time t ref - 64 - 64 ms
HY5V16CF rev. 0.0/jun.01 9 device operating option table HY5V16CF-h HY5V16CF-s cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.5ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 2.5ns 100mhz(10ns) 3clks 3clks 6clks 9clks 3clks 6ns 2.5ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 8clks 3clks 6ns 2.5ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
HY5V16CF rev. 0.0/jun.01 10 command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x h x x x x x l h h h bank active h x l l h h x ra v read h x l h l h x ca l v read with autoprecharge h write h x l h l l x ca l v write with autoprecharge h precharge all banks h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x self refresh 1 entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
HY5V16CF rev. 0.0/jun.01 11 package information 60 ball fd-bga package

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